A 3D electronic module comprises a stack of electronic wafer levels interconnected in three dimensions using the lateral faces of the stack to produce the connections between the wafer levels.
It is known to electrically connect the wafer levels together by conductors located on the lateral faces of the stack, i.e. on the edges of the wafer levels. The number of conductors present on a lateral face is therefore limited by the area of said face.
Moreover, it is desirable to be able to fabricate 3D modules collectively so as to reduce their cost.
Consequently, there remains at the present time a need for a process for fabricating 3D electronic modules that simultaneously meets all the aforementioned requirements, namely an increase in the number of electrical connections between the wafer levels and collective fabrication.
These conductors are spaced apart typically by a pitch of 200 μm. The number of conductors present on a lateral face is therefore limited by the area of the latter divided by the pitch.
The principle of the invention is to divide the pitch of the conductors. This is obtained by creating vias in the electronic module without being limited to the lateral faces thereof.